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myson-century technology MTV412M (rev 0.9) 8051 embedded monitor controller 128k flash type with isp revision 0.9 - 1 - april 2002 features ? 8051 core, 12mhz operating frequency with double cpu clock option ? 0.35um process; 3.3v/5v power supply; 5v i/o tolerant ? 1024-byte ram; 128k-byte program flash-rom support in system programming (isp) without boot code ? maximum 14 channels of pwm dac ? maximum 38 (44-pin) or 36 (42-pin) i/o pins ? sync processor for composite separation/insertion, h/v polarity/frequency check and polarity adjustment ? clock output to drive other devices ? built-in low power reset circuit ? compliant with vesa ddc1/2b/2bi/2b+ standard ? triple slave iic addresses; two h/w auto transfer ddc1/ddc2x data for both d-sub and dvi interfaces ? single master iic interface for internal device communication ? maximum 4-channel 8-bit a/d converter ? flash-rom program code protection selection ? 42-pin sdip or 44-pin plcc/pqfp package general descriptions the MTV412M micro-controller is an 8051 cpu core embedded device targeted for lcd monitor, lcd tv or smart panel applications. it includes an 8051 cpu core, 1024-byte sram, on-chip 16k-bit eeprom, 14 pwm dacs, vesa ddc for both d-sub and dvi interfaces, 4-channel 8-bit adc, hardware isp without boot code and a 128k-byte internal program flash-rom in 42-pin sdip, 44-pin plcc/pqfp package. this datasheet contains new product information. myson technology reserves the rights to modify the product specification witho ut notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the pr oduct. p0.0-7 p2.0-3 rd w r ale int1 8051 core p1.0-7 p3.0-2 p3.4 rst x1 x2 adc a d0-3 pwm dac da0-13 xfr p0.0-7 p2.0-3 rd wr ale int1 auxram & ddcram1 & ddcram2 ddc & iic interface iscl isd a hscl1 hsda1 hscl2 hsda2 p6.0-7 p5.0-6 aux i/o p4.0-2 p7.0-7 hsync vsync hblan k vblan k h/vsync control hclamp vcoast 16k-bit eeprom cko
myson-century technology MTV412M (rev 0.9) revision 0.9 - 2 - april 2002 pin connection MTV412M 44 pin plcc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 p1.6 24 p1.7 p6.1/ad1 p1.5 p6.0/ad0 hsda/p3.1/txd p1.1 p3.2/int0 p1.2 p1.3 p1.4 23 22 21 20 28 27 26 25 hscl2/p7.5 6 5 4 3 2 1 44 43 42 41 40 hsda2/p7.6 vdd3 da0/p5.0 da1/p5.1 da2/p5.2 vsync/p7.4 hsync/p7.3 da3/p5.3 da4/p5.4 da5/p5.5 19 18 rst vdd vss x2 x1 isda/p3.4/t0 iscl/p7.7 vcoast/p4.2 p6.2/ad2 p1.0 p6.3/ad3 p6.4/da10 hscl/p3.0/rxd p6.5/da11 p6.6/da12 da8/p7.1 da9/p7.2 hblank/p4.1 da7/p7.0/hclamp da6/p5.6/cko vblank/p4.0 p6.7/da13 MTV412M 42 pin sdip da2/p5.2 40 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 da1/p5.1 da0/p5.0 rst vdd vss vdd3 hsda2/p7.6 hscl2/p7.5 hsync/p7.3 da3/p5.3 vsync/p7.4 da4/p5.4 da8/p7.1 da9/p7.2 da5/p5.5 hblank/p4.1 da7/p7.0/hclamp da6/p5.6/cko vblank/p4.0 42 41 isda/p3.4/t0 iscl/p7.7 p4.2 p6.2/ad2 p1.0 p1.1 p3.2/int0 p1.2 p1.3 p1.4 x2 x1 p6.6/da12 p6.5/da11 hscl1/p3.0/rxd hsda1/p3.1/txd p6.4/da10 p6.0/ad0 p1.7 p1.6 p6.1/ad1 p1.5
myson-century technology MTV412M (rev 0.9) revision 0.9 - 3 - april 2002 pin configuration a ?cmos output pin? means it can sink and drive at least 4ma current. it is not recommended to use such pin as input function. a ?open drain pin? means it can sink at least 4ma current but only drive 10~20ua to vdd. it can be used as input or output function and needs an external pull up resistor. a ?8051 standard pin? is a pseudo open drain pin. it can sink at least 4ma current when output is at low level, and drives at least 4ma current for 160ns when output transits from low to high, then keeps driving at 100ua to maintain the pin at high level. it can be used as input or output function. it needs an external pull up resistor when driving heavy load device. power configuration the MTV412M can work on 5v or 3.3v power supply system. in 5v power system, the vdd pin is connected to 5v power and the vdd3 needs an external capacitor, all output pins can swing from 0~5v, input pins can accept 0~5v input range. and adc conversion range is 5v. however, x1 and x2 pins must be kept below 3.3v. in 3.3v power system, the vdd and vdd3 are connected to 3.3v power, all output pins swing from 0~3.3v, hsync, vsync and open drain pin can accept 0~5v input range, other pins must be kept below 3.3v. and the adc conversion range is 3.3v. 8051 standard pin 4ma 4ma output data pin cmos output pin open drain pin 2 osc period delay 4ma 10ua output data 120ua pin 4ma input data no current 4ma output data pin input data vdd vdd3 3.3v vdd vdd3 MTV412M in 3.3v system 5v 10u MTV412M in 5v system vdd vdd3
myson-century technology MTV412M (rev 0.9) revision 0.9 - 4 - april 2002 pin description pin no. name 42 44 type description vdd3 4 4 o 3.3v core power vdd 8 8 - 5v or 3.3v positive power supply vss 9 10 - ground x2 10 11 o oscillator output x1 11 12 i oscillator input rst 7 7 i active high reset da0/p5.0 3 3 i/o pwm dac output / general purpose i/o (cmos) da1/p5.1 2 2 i/o pwm dac output / general purpose i/o (cmos) da2/p5.2 1 1 i/o pwm dac output / general purpose i/o (cmos) da3/p5.3 40 42 i/o pwm dac output / general purpose i/o (cmos) da4/p5.4 39 41 i/o pwm dac output / general purpose i/o (cmos) da5/p5.5 38 40 i/o pwm dac output / general purpose i/o (cmos) da6/p5.6/cko 32 34 i/o pwm dac output / general purpose i/o / oscillator freq. clock output (cmos) da7/p7.0/hclamp 33 35 i/o pwm dac output / general purpose i/o / hsync clamp pulse output (cmos) da8/p7.1 37 39 i/o pwm dac output / general purpose i/o (open drain) da9/p7.2 36 38 i/o pwm dac output / general purpose i/o (open drain) hscl1/p3.0/rxd 28 29 i/o slave iic 1 clock / general purpose i/o / rxd (open drain) hsda1/p3.1/txd 27 28 i/o slave iic 1 data / general purpose i/o / txd (open drain) hscl2/p7.5 6 6 i/o slave iic 2 clock / general purpose i/o (open drain) hsda2/p7.6 5 5 i/o slave iic 2 data / general purpose i/o (open drain) p3.2/int0 18 19 i/o general purpose i/o / int0 (8051 standard) isda/p3.4/t0 12 13 i/o master iic data / general purpose i/o / t0 (open drain) iscl/p7.7 13 14 i/o master iic clock / general purpose i/o (open drain) p1.0 16 17 i/o general purpose i/o (cmos output or 8051 standard) p1.1 17 18 i/o general purpose i/o (cmos output or 8051 standard) p1.2 19 20 i/o general purpose i/o (cmos output or 8051 standard) p1.3 20 21 i/o general purpose i/o (cmos output or 8051 standard) p1.4 21 22 i/o general purpose i/o (cmos output or 8051 standard) p1.5 22 23 i/o general purpose i/o (cmos output or 8051 standard) p1.6 23 24 i/o general purpose i/o (cmos output or 8051 standard) p1.7 24 25 i/o general purpose i/o (cmos output or 8051 standard) p6.0/ad0 26 27 i/o general purpose i/o / adc input (cmos) p6.1/ad1 25 26 i/o general purpose i/o / adc input (cmos) p6.2/ad2 15 16 i/o general purpose i/o / adc input / half hsync input (cmos) p6.3/ad3 - 9 i/o general purpose i/o / adc input (cmos) p6.4/da10 29 30 i/o general purpose i/o / pwm dac output (cmos) p6.5/da11 30 31 i/o general purpose i/o / pwm dac output (cmos) p6.6/da12 31 32 i/o general purpose i/o / pwm dac output (cmos) p6.7/da13 - 33 i/o general purpose i/o / pwm dac output (cmos) vblank/p4.0 34 36 o vertical blank (cmos) / general purpose output (cmos) hblank/p4.1 35 37 o horizontal blank (cmos) / general purpose output (cmos) p4.2 14 15 o general purpose output (cmos) hsync/p7.3 41 43 i/o horizontal sync or composite sync input / general purpose i/o (cmos) vsync/p7.4 42 44 i/o vertical sync input / general purpose i/o (cmos)
myson-century technology MTV412M (rev 0.9) revision 0.9 - 5 - april 2002 functional descriptions 1. 8051 cpu core the cpu core of MTV412M is compatible with the industry standard 8051, which includes 256 bytes ram, special function registers (sfr), two timers, five interrupt sources and a serial interface. the cpu core fetches its program code from the 128k bytes flash in MTV412M. it uses port0 and port2 to access the ?external special function register? (xfr) and external auxiliary ram (auxram). the cpu core can run at double rate when fclke is set. once the bit is set, the cpu runs as if a 24mhz x?tal is applied on MTV412M, but the peripherals (iic, ddc, h/v processor) still run at the original frequency. note: all registers listed in this document reside in 8051?s external ram area (xfr). for internal ram memory map, please refer to 8051 spec. 2. memory allocation 2.1 internal special function registers (sfr) the sfr is a group of registers that are the same as standard 8051. 2.2 internal ram there are total 256 bytes internal ram in MTV412M, the same as standard 8052. 2.3 external special function registers (xfr) the xfr is a group of registers allocated in the 8051 external ram area f00h - fffh. these registers are used for special functions. programs can use "movx" instruction to access these registers. 2.4 auxiliary ram (auxram) there are total 256 bytes auxiliary ram allocated in the 8051 external ram area 800h - 8ffh. programs can use "movx" instruction to access the auxram. 2.5 dual port ram (ddcram1 & ddcram2) there are 2x256 bytes dual port ram allocated in the 8051 external ram area 900h - 9ffh & e00h - effh for h/w auto transfer ddc. the external ddc1/2 host can access the ram as if two 24lc02 eeproms are connected onto the interface. the hscl1, hsda1 pins can access ddcram1 directly. and the hscl2, hsda2 pins can access ddcram2 directly. programs can also use "movx" instruction to access these ram. 00h 7fh 80h ffh internal ram accessible by indirect addressing only (using mov a,@ri instruction) internal ram accessible by direct and indirect addressing sfr accessible by direct addressing 800h 8ffh auxram accessible by indirect external ram addressing (using movx instruction f00h fffh xfr accessible by indirect external ram addressing (using movx instruction) e00h effh ddcram1 accessible by indirect external ram addressing (using movx instruction) 900h 9ffh ddcram2 accessible by indirect external ram addressing (using movx instruction)
myson-century technology MTV412M (rev 0.9) revision 0.9 - 6 - april 2002 3. chip configuration the chip configuration registers define configuration of the chip and function of the pins. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod f50h(w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod f51h(w) p56e p55e p54e p53e p52e p51e p50e padmod f52h(w) hiic1e iiice hiic2e ckoe hclpe p42e p41e p40e padmod f53h(w) p56oe p55oe p54oe p53oe p52oe p51oe p50oe padmod f54h(w) p67oe p66oe p65oe p64oe p63oe p62oe p61oe p60oe padmod f55h(w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 option f56h(w) pwmf div253 fclke enscl msel miicf1 miicf0 padmod f5eh(w) p74e p73e p72e p71e p70e padmod f5fh(w) p77oe p76oe p75oe p74oe p73oe p72oe p71oe p70oe padmod (w) : pad mode control registers. (all are "0" in chip reset, except for hiic1e bit) da13e = 1 pin ?p6.7/da13? is da13. = 0 pin ?p6.7/da13? is p6.7. da12e = 1 pin ?p6.6/da12? is da12. = 0 pin ?p6.6/da12? is p6.6. da11e = 1 pin ?p6.5/da11? is da11. = 0 pin ?p6.5/da11? is p6.5. da10e = 1 pin ?p6.4/da10? is da10. = 0 pin ?p6.4/da10? is p6.4. ad3e = 1 pin ?p6.3/ad3? is ad3. = 0 pin ?p6.3/ad3? is p6.3. ad2e = 1 pin ?p6.2/ad2? is ad2. = 0 pin ?p6.2/ad2? is p6.2. ad1e = 1 pin ?p6.1/ad1? is ad1. = 0 pin ?p6.1/ad1? is p6.1. ad0e = 1 pin ?p6.0/ad0? is ad0. = 0 pin ?p6.0/ad0? is p6.0. p56e = 1 pin ?da6/p5.6/cko? is p5.6. = 0 pin ?da6/p5.6/cko? is da6/cko selected by ckoe bit. p55e = 1 pin ?da5/p5.5? is p5.5. = 0 pin ?da5/p5.5? is da5. p54e = 1 pin ?da4/p5.4? is p5.4. = 0 pin ?da4/p5.4? is da4. p53e = 1 pin ?da3/p5.3? is p5.3. = 0 pin ?da3/p5.3? is da3. p52e = 1 pin ?da2/p5.2? is p5.2. = 0 pin ?da2/p5.2? is da2. p51e = 1 pin ?da1/p5.1? is p5.1. = 0 pin ?da1/p5.1? is da1. p50e = 1 pin ?da0/p5.0? is p5.0. = 0 pin ?da0/p5.0? is da0. hiic1e = 1 pin ?hscl1/p3.0/rxd? is hscl1; pin ?hsda1/p3.1/txd? is hsda1. = 0 pin ?hscl1/p3.0/rxd? is p3.0/rxd; pin ?hsda1/p3.1/txd? is p3.1/txd. iiice = 1 pin ?isda/p3.4/t0? is isda; pin ?iscl/p7.7? is iscl. = 0 pin ?isda/p3.4/t0? is p3.4/t0; pin ?iscl/p7.7? is p7.7. hiic2e = 1 pin ?hscl2/p7.5? is hscl2. pin ?hsda2/p7.6? is hsda6. = 0 pin ?hscl2/p7.5? is p7.5. pin ?hsda2/p7.6? is p7.6.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 7 - april 2002 ckoe = 1 pin ?da6/p5.6/cko is cko if p56e = 0. = 0 pin ?da6/p5.6/cko? is da6 if p56e = 0. hclpe = 1 pin ?da7/p7.0/hclamp? is hclamp if p70e = 0. = 0 pin ?da7/p7.0/hclamp? is da7 if p70e = 0. p42e = 1 pin ?p4.2? is p4.2. = 0 reserved p41e = 1 pin ?hblank/p4.1? is p4.1. = 0 pin ?hblank/p4.1? is hblank. p40e = 1 pin ?vblank/p4.0? is p4.0. = 0 pin ?vblank/p4.0? is vblank. p56oe = 1 p5.6 is output pin. = 0 p5.6 is input pin. p55oe = 1 p5.5 is output pin. = 0 p5.5 is input pin. p54oe = 1 p5.4 is output pin. = 0 p5.4 is input pin. p53oe = 1 p5.3 is output pin. = 0 p5.3 is input pin. p52oe = 1 p5.2 is output pin. = 0 p5.2 is input pin. p51oe = 1 p5.1 is output pin. = 0 p5.1 is input pin. p50oe = 1 p5.0 is output pin. = 0 p5.0 is input pin. p67oe = 1 p6.7 is output pin. = 0 p6.7 is input pin. p66oe = 1 p6.6 is output pin. = 0 p6.6 is input pin. p65oe = 1 p6.5 is output pin. = 0 p6.5 is input pin. p64oe = 1 p6.4 is output pin. = 0 p6.4 is input pin. p63oe = 1 p6.3 is output pin. = 0 p6.3 is input pin. p62oe = 1 p6.2 is output pin. = 0 p6.2 is input pin. p61oe = 1 p6.1 is output pin. = 0 p6.1 is input pin. p60oe = 1 p6.0 is output pin. = 0 p6.0 is input pin. cop17 = 1 pin ?p1.7? is cmos output. = 0 pin ?p1.7? is 8051 standard i/o. cop16 = 1 pin ?p1.6? is cmos output. = 0 pin ?p1.6? is 8051 standard i/o. cop15 = 1 pin ?p1.5? is cmos output. = 0 pin ?p1.5? is 8051 standard i/o. cop14 = 1 pin ?p1.4? is cmos output. = 0 pin ?p1.4? is 8051 standard i/o. cop13 = 1 pin ?p1.3? is cmos output. = 0 pin ?p1.3? is 8051 standard i/o. cop12 = 1 pin ?p1.2? is cmos output. = 0 pin ?p1.2? is 8051 standard i/o.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 8 - april 2002 cop11 = 1 pin ?p1.1? is cmos output. = 0 pin ?p1.1? is 8051 standard i/o. cop10 = 1 pin ?p1.0? is cmos output. = 0 pin ?p1.0? is 8051 standard i/o. p74e = 1 pin ?vsync/p7.4? is p7.4. = 0 pin ?vsync/p7.4? is vsync. p73e = 1 pin ?hsync/p7.3? is p7.3. = 0 pin ?hsync/p7.3? is hsync. p72e = 1 pin ?da9/p7.2? is p7.2. = 0 pin ?da9/p7.2? is da9. p71e = 1 pin ?da8/p7.1? is p7.1. = 0 pin ?da8/p7.1? is da8. p70e = 1 pin ?da7/p7.0/hclamp? is p7.0. = 0 pin ?da7/p7.0/hclamp" is da7/hclamp selected by hclpe bit. p77oe = 1 p7.7 is output pin. = 0 p7.7 is input pin. p76oe = 1 p7.6 is output pin. = 0 p7.6 is input pin. p75oe = 1 p7.5 is output pin. = 0 p7.5 is input pin. p74oe = 1 p7.4 is output pin. = 0 p7.4 is input pin. p73oe = 1 p7.3 is output pin. = 0 p7.3 is input pin. p72oe = 1 p7.2 is output pin. = 0 p7.2 is input pin. p71oe = 1 p7.1 is output pin. = 0 p7.1 is input pin. p70oe = 1 p7.0 is output pin. = 0 p7.0 is input pin. option (w) : chip option configuration (all are "0" in chip reset). pwmf = 1 selects 94khz pwm frequency. = 0 selects 47khz pwm frequency. div253 = 1 pwm pulse width is 253-step resolution. = 0 pwm pulse width is 256-step resolution. fclke = 1 cpu is running at double rate = 0 cpu is running at normal rate enscl = 1 enable slave iic block to hold hscl pin low while MTV412M is unable to catch-up with the external master's speed. msel = 1 master iic block connect to hscl1/hsda1 pins. = 0 master iic block connect to iscl/isda pins. miicf1,miicf0 = 1,1 selects 400khz master iic frequency. = 1,0 selects 200khz master iic frequency. = 0,1 selects 50khz master iic frequency. = 0,0 selects 100khz master iic frequency.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 9 - april 2002 4. i/o ports 4.1 port1 port1 is a group of pseudo open drain pins or cmos output pins. it can be used as general purpose i/o. behavior of port1 is the same as standard 8051. 4.2 p3.0-2, p3.4 if these pins are not set as iic pins, port3 can be used as general purpose i/o, interrupt, uart and timer pins. behavior of port3 is the same as standard 8051. 4.3 port4, port5, port6 and port7 port5, port6 and port7 are used as general purpose i/o. s/w needs to set the corresponding p5(n)oe, p6(n)oe and p7(n)oe to define whether these pins are input or output. port4 is pure output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port5 f30h(r/w) p50 port5 f31h(r/w) p51 port5 f32h(r/w) p52 port5 f33h(r/w) p53 port5 f34h(r/w) p54 port5 f35h(r/w) p55 port5 f36h(r/w) p56 port6 f38h(r/w) p60 port6 f39h(r/w) p61 port6 f3ah(r/w) p62 port6 f3bh(r/w) p63 port6 f3ch(r/w) p64 port6 f3dh(r/w) p65 port6 f3eh(r/w) p66 port6 f3fh(r/w) p67 port4 f58h(w) p40 port4 f59h(w) p41 port4 f5ah(w) p42 port7 f70h(r/w) p70 port7 f71h(r/w) p71 port7 f72h(r/w) p72 port7 f73h(r/w) p73 port7 f74h(r/w) p74 port7 f75h(r/w) p75 port7 f76h(r/w) p76 port7 f77h(r/w) p77 port5 (r/w) : port 5 data input/output value. port6 (r/w) : port 6 data input/output value. port4 (w) : port 4 data output value. port7 (r/w) : port 7 data input/output value. 5. pwm dac each output pulse width of pwm dac converter is controlled by an 8-bit register in xfr. the frequency of
myson-century technology MTV412M (rev 0.9) revision 0.9 - 10 - april 2002 pwm clock is 47khz or 94khz, selected by pwmf. and the total duty cycle step of these dac outputs is 253 or 256, selected by div253. if div253=1, writing fdh/feh/ffh to dac register generates stable high output. if div253=0, the output pulses low at least once even if the dac register's content is ffh. writing 00h to dac register generates stable low output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 f20h(r/w) pulse width of pwm dac 0 da1 f21h(r/w) pulse width of pwm dac 1 da2 f22h(r/w) pulse width of pwm dac 2 da3 f23h(r/w) pulse width of pwm dac 3 da4 f24h(r/w) pulse width of pwm dac 4 da5 f25h(r/w) pulse width of pwm dac 5 da6 f26h(r/w) pulse width of pwm dac 6 da7 f27h(r/w) pulse width of pwm dac 7 da8 f28h(r/w) pulse width of pwm dac 8 da9 f29h(r/w) pulse width of pwm dac 9 da10 f2ah(r/w) pulse width of pwm dac 10 da11 f2bh(r/w) pulse width of pwm dac 11 da12 f2ch(r/w) pulse width of pwm dac 12 da13 f2dh(r/w) pulse width of pwm dac 13 da0-13 (r/w) : the output pulse width control for da0-13. * all of pwm dac converters are centered with value 80h after power on. 6. h/v sync processing the h/v sync processing block performs the functions of composite signal separation/insertion. sync inputs presence check, frequency counting, polarity detection and control, as well as the protection of vblank output while vsync speeds up in high ddc communication clock rate. based on the digital filter, the hsync present and frequency function block treat any pulse longer than the specified time period as pulse, and the specified time period is controlled by (df1,df0) bits. the vsync digital filter has no control bit. it works as (df1,df0) = (0, 0) of hsync.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 11 - april 2002 6.1 composite sync separation/insertion the MTV412M continuously monitors the input hsync. if the vertical sync pulse can be extracted from the input, a cvpre flag is set and users can select the extracted "cvsync" for the source of polarity check, frequency count, and vblank output. the cvsync then has 8us delay compared to the original signal. the MTV412M can also insert pulse to hblank output during composite vsync?s active time. the width of insert pulse is 1/8 hsync period and the insertion frequency can adapt to original hsync. the insert pulse of hblank can be disabled or enabled by setting ?nohins? control bit. if ?nohins? bit is set to "1", hblank output will be same as hsync input (of course, polarity can be controlled by hbpl bit). 6.2 h/v frequency counter MTV412M can discriminate hsync/vsync frequency and save the information in xfrs. the 14-bit hcounter counts the time of 64xhsync period, then loads the result into the hcnth/hcntl latch. the output value is then [(128000000/h-freq) - 1], updated once per vsync/cvsync period when vsync/cvsync is present or continuously updated when vsync/cvsync is non-present. the 12-bit vcounter counts the time between two vsync pulses, then loads the result into the vcnth/vcntl latch. the output value is then (62500/v-freq), updated every vsync/cvsync period. an extra overflow bit indicates the condition of h/v counter overflow. the vfchg/hfchg interrupt is set when vcnt/hcnt value changes or overflows. table 6.2.1 and table 6.2.2 show the hcnt/vcnt value under the operations of 12mhz. hpol cvpre vbpl vsync digital filter polarity check & sync seperator vpre present check vfreq vpol polarity check & freq. count xor vblank vself xor hsync digital filter cvsync present check hpre hfreq present check & freq. count xor hbpl xor hblank composite pulse insert h/v sync processor block diagram
myson-century technology MTV412M (rev 0.9) revision 0.9 - 12 - april 2002 timing relationship of composite sync signal separation/insertion when "nohins" = 0 double serrated + e q ual. h xor v extrhs for h or v & h xor v & single serrated 1/8 hsync p eriod insert hsync p ulse hsync vsync h or v single serrated 8us extrvs for h or v & single serrated 8us extrvs for h xor v 8us 8us extrvs for double serrated + equal. 8us 8us extrhs for double serrated + equal. 1/8 hsync p eriod insert hsync p ulse 8us vcoast for h or v & h xor v & single serrated 1/2 hsync period vcoast for double serrated + equal. 3/4 hsync period 1/2 hsync period
myson-century technology MTV412M (rev 0.9) revision 0.9 - 13 - april 2002 6.2.1 h-freq table output value (14 bits) h-freq(khz) 12mhz osc (hex / dec) 1 31.5 0fdeh / 4062 2 37.5 0d54h / 3412 3 43.3 0b8bh / 2955 4 46.9 0aa8h / 2728 5 53.7 094fh / 2383 6 60.0 0854h / 2132 7 68.7 0746h / 1862 8 75.0 06aah / 1706 9 80.0 063fh / 1599 10 85.9 05d1h / 1489 11 93.8 0554h / 1364 12 106.3 04b3h / 1203 6.2.2 v-freq table output value (12bits) v-freq(hz) 12mhz osc (hex / dec) 1 56 45ch / 1116 2 60 411h / 1041 3 70 37ch / 892 4 72 364h / 868 5 75 341h / 833 6 85 2dfh / 735 6.3 h/v present check the hpresent function checks the input hsync pulse, and the hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. the vpresent function checks the input vsync pulse, and the vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz. the hprchg interrupt is set when the hpre value changes. the vprchg interrupt is set when the vpre/cvpre value change. 6.4 h/v polarity detect the polarity functions detect the input hsync/vsync high and low pulse duty cycle. if the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. the hplchg interrupt is set when the hpol value changes. the vplchg interrupt is set when the vpol value changes. 6.5 output hblank/vblank control and polarity adjust the hblank is the mux output of hsync and composite hpulse. the vblank is the mux output of vsync and cvsync. the mux selection and output polarity are s/w controllable. the vblank output is cut off when vsync frequency is over 250hz. the hblank/vblank shares the output pin with p4.1/ p4.0. 6.6 vsync coast pulse output this output pin define the period of adc pll which is needed to disable locking for composite sync. the output polarity of vcoast are s/w controllable. 6.7 hsync clamp pulse output the hclamp output is activated by setting ?hclpe? control bit. the leading edge position, pulse width and polarity of hclamp are s/w controllable. 6.8 vsync interrupt the MTV412M checks the vsync input pulse and generates an interrupt at its leading edge. the vsync flag is set each time when MTV412M detects a vsync pulse. he flag is cleared by s/w writing a "0".
myson-century technology MTV412M (rev 0.9) revision 0.9 - 14 - april 2002 6.9 h/v sync processor register reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hvstus f40h(r) cvpre hpol vpol hpre vpre hoff voff hcnth f41h(r) hovf hf13 hf12 hf11 hf10 hf9 hf8 hcntl f42h(r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth f43h(r) vovf vf11 vf10 vf9 vf8 vcntl f44h(r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 hvctr0 f40h(w) c1 c0 nohins hbpl vbpl hvctr2 f42h(w) hvctr3 f43h(w) clpeg clppo clpw2 clpw1 clpw0 hvctr4 f44h(w) df1 df0 intflg f48h(r/w) hprchg vprchg hplchg vplchg hfchg vfchg vsync inten f49h(w) ehpr evpr ehpl evpl ehf evf evsync hvstus (r) : the status of polarity, present and static level for hsync and vsync. cvpre = 1 the extracted cvsync is present. = 0 the extracted cvsync is not present. h pol = 1 hsync input is positive polarity. = 0 hsync input is negative polarity. v pol = 1 vsync (cvsync) is positive polarity. = 0 vsync (cvsync) is negative polarity. h pre = 1 hsync input is present. = 0 hsync input is not present. v pre = 1 vsync input is present. = 0 vsync input is not present. h off* = 1 off level of hsync input is high. = 0 off level of hsync input is low. v off* = 1 off level of vsync input is high. = 0 off level of vsync input is low. *h off and v off are valid when h pre=0 or v pre=0. hcnth (r) : h-freq counter's high bits. hovf = 1 h-freq counter is overflowed, this bit is cleared by h/w when condition removed. hf13 - hf8 : 6 high bits of h-freq counter. hcntl (r) : h-freq counter's low byte. vcnth (r) : v-freq counter's high bits. vovf = 1 v-freq counter is overflowed, this bit is cleared by h/w when condition removed. vf11 - 8 : 4 high bits of v-freq counter. vcntl (r) : v-freq counter's low byte. hvctr0 (w) : h/v sync processor control register 0. c1, c0 = 1,1 selects cvsync as the polarity, freq and vblank source. = 1,0 selects vsync as the polarity, freq and vblank source. = 0,0 disables composite function. = 0,1 h/w automatically switches to cvsync when cvpre=1 and vspre=0. nohins = 1 hblank has no insert pulse in composite mode. = 0 hblank has insert pulse in composite mode. hb pl = 1 negative polarity hblank output. = 0 positive polarity hblank output.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 15 - april 2002 vb pl = 1 negative polarity vblank output. = 0 positive polarity vblank output. hvctr3 (w) : hsync clamp pulse control register. clpeg = 1 clamp pulse follows hsync leading edge. = 0 clamp pulse follows hsync trailing edge. clppo = 1 positive polarity clamp pulse output. = 0 negative polarity clamp pulse output. clpw2 : clpw0 : pulse width of clamp pulse is [(clpw2:clpw0) + 1] x 0.167 s for 12mhz x?tal selection. hvctr4 (w) : df1, df0 : = 0,0 the digital filter will treat any hsync pulse shorter than one osc period (83.33ns) as noise, between one and two osc period (83.33ns to 166.67ns) as unknown region, and longer than two osc period (166.67ns) as pulse. = 0,1 the digital filter will treat any hsync pulse shorter than half osc period (41.66ns) as noise, between half and one osc period (41.66ns to 83.33ns) as unknown region, and longer than one osc period (83.33ns) as pulse. = 1,x disable the digital filter for hsync. intflg (w) : interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the int1 source of 8051 core will be driven by a zero level. software must clear this register while serving the interrupt routine. hprchg= 1 no action. = 0 clears hsync presence change flag. vprchg= 1 no action. = 0 clears vsync presence change flag. hplchg = 1 no action. = 0 clears hsync polarity change flag. vplchg = 1 no action. = 0 clears vsync polarity change flag. hfchg = 1 no action. = 0 clears hsync frequency change flag. vfchg = 1 no action. = 0 clears vsync frequency change flag. vsync = 1 no action. = 0 clears vsync interrupt flag. intflg (r) : interrupt flag. hprchg= 1 indicates a hsync presence change. vprchg= 1 indicates a vsync presence change. hplchg = 1 indicates a hsync polarity change. vplchg = 1 indicates a vsync polarity change. hfchg = 1 indicates a hsync frequency change or counter overflow. vfchg = 1 indicates a vsync frequency change or counter overflow. vsync = 1 indicates a vsync interrupt. inten (w) : interrupt enable. ehpr = 1 enables hsync presence change interrupt. evpr = 1 enables vsync presence change interrupt. ehpl = 1 enables hsync polarity change interrupt. evpl = 1 enables vsync polarity change interrupt. ehf = 1 enables hsync frequency change / counter overflow interrupt.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 16 - april 2002 evf = 1 enables vsync frequency change / counter overflow interrupt. evsync = 1 enables vsync interrupt. 7. ddc & iic interface 7.1 ddc1/ddc2x mode, ddcram1/ddcram2 and slavea1/slavea2 block the MTV412M supports vesa ddc for both d-sub and dvi interfaces through hscl1/hsda1 and hscl2/hsda2 pins. the hscl1/hsda1 pins access ddcram1 by slavea1, and the hscl2/hsda2 pins access ddcram2 by slavea2. the MTV412M enters ddc1 mode for both ddc channels after reset. in this mode, vsync is used as data clock. the hscl1/hscl2 pin should remain at high. the data output to the hsda1/hsda2 pin is taken from a shift register in MTV412M. the shift register automatically fetches edid data from the lower 128 bytes of the dual port ram (ddcram1/ddcram2), then sends it in 9-bit packet formats inclusive of a null bit (=1) as packet separator. s/w may enable/disable the ddc1 function by setting/clearing the ddc1en control bit. the MTV412M switches to ddc2x mode when it detects a high to low transition on the hscl1/hscl2 pin. in this mode, the slavea1/slavea2 iic block automatically transmits/receives data to/from the iic master. the transmitted/received data is taken-from/saved-to the ddcram1/ddcram2. in simple words, MTV412M can behaves as two 24lc02 eeproms. the only thing s/w needs to do is to write the edid data to ddcram1/ddcram2. these slave address of slavea1/slavea2 block can be chosen by s/w as 5- bit, 6-bit or 7-bit. for example, if s/w chooses 5-bit slave address as 10100b, the slavea1 iic block then responds to slave address 10100xxb. the slavea1/slavea2 can be enabled/disabled by setting/clearing the enslva1/enslva2 bit. the lower/upper ddcram1/ddcram2 can/cannot be written by the iic master by setting/clearing the en128w/en256w bit. besides, if the only128 control bit is set, the slavea1/slavea2 only accesses the lower 128 bytes of the ddcram1/ddcram2. the MTV412M returns to ddc1 mode if hscl1 is kept high for 128 vsync clock period. however, it locks in ddc2b mode if a valid iic address (1010xxxb) has been detected on hscl1/hsda1 buses. the ddc2 flag reflects the current ddc status, s/w may clear it by writing a "0" to it. 7.2 slaveb block the slaveb iic block is connected to hsda1 and hscl1 pins only. this block can receive/transmit data using iic protocols. s/w may write the slvbadr register to determine the slave addresses. in receive mode, the block first detects iic slave address matching the condition then issues a slvbmi interrupt. the data from hsda1 is shifted into shift register then written to rcbbuf register when a data byte is received. the first byte loaded is word address (slave address is dropped). this block also generates a rcbi (receives buffer full interrupt) every time when the rcbbuf is loaded. if s/w is not able to read out the rcbbuf in time, the next byte in shift register is not written to rcbbuf and the slave block returns nack to the master. this feature guarantees the data integrity of communication. the wadrb flag can tell s/w whether the data in rcbbuf is a word address or not. in transmit mode, the block first detects iic slave address matching the condition, then issues a slvbmi interrupt. in the meantime, the data pre-stored in the txbbuf is loaded into shift register, resulting in txbbuf emptying and generates a txbi (transmit buffer empty interrupt). s/w should write the txbbuf a new byte for the next transfer before shift register empties. a failure of this process causes data corrupt. the txbi occurs every time when shift register reads out the data from txbbuf. the slvbmi is cleared by writing "0" to corresponding bit in intflg register. the rcbi is cleared by reading out rcbbuf. the txbi is cleared by writing txbbuf. *please refer to the attachments about "slave iic block timing". 7.3 master mode iic function block the master mode iic block can be connected to the isda /iscl pins or the hsda1/hscl1 pins, selected by msel control bit. its speed can be selected within the range of 50khz-400khz by s/w setting the miicf1/miicf0 control bit. the software program can access the external iic device through this interface. a summary of master iic access is illustrated as follows.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 17 - april 2002 7.3.1. to write iic device 1. write mbuf the slave address. 2. set s bit to start. 3. after the MTV412M transmits this byte, a mbufi interrupt is triggered. 4. programs can write mbuf to transfer next byte or set p bit to stop. * please refer to the attachments about "master iic transmit timing". 7.3.2. to read iic device 1. write mbuf the slave address. 2. set s bit to start. 3. after the MTV412M transmits this byte, a mbufi interrupt is triggered. 4. set or reset the macko flag according to the iic protocol. 5. read out mbuf the useless byte to continue the data transfer. 6. after the MTV412M receives a new byte, the mbufi interrupt is triggered again. 7. read mbuf also trigger the next receive operation, but set p bit before read can terminate the operation. * please refer to the attachments about "master iic receive timing". reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr f00h (r/w) ddc2a1 ddc2a2 macko p s iicstus f01h (r) wadrb slvrwb sackin slvs mackin intflg f03h (r) txbi rcbi slvbmi stopi restai wslva1i wslva2i mbufi intflg f03h (w) slvbmi stopi restai wslva1i wslva2i mbufi inten f04h (w) etxbi ercbi eslvbmi estopi erestai ewslva1i ewslva2i embufi mbuf f05h (r/w) master iic receive/transmit data buffer ddcctra1 f06h (w) ddc1en en128w en256w only128 slva1bs1 slva1bs0 slva1adr f07h (w) enslva1 slave a1 iic address rcbbuf f08h (r) slave b iic receive buffer txbbuf f08h (w) slave b iic transmit buffer slvbadr f09h (w) enslvb slave b iic address ddcctra2 f86h (w) ddc1en en128w en256w only128 slva2bs1 slva2bs0 slva2adr f87h (w) enslva2 slave a2 iic address iicctr (r/w) : iic interface status/control register. ddc2a1 = 1 ddc2 is active for hscl1/hsda1 pins. = 0 MTV412M remains in ddc1 mode for hscl1/hsda1 pins. ddc2a2 = 1 ddc2 is active for hscl2/hsda2 pins. = 0 MTV412M remains in ddc1 mode for hscl2/hsda2 pins. macko = 1 in master receive mode, nack is returned by MTV412M. = 0 in master receive mode, ack is returned by MTV412M. s, p = , 0 start condition when master iic is not during transfer. = x, stop condition when master iic is not during transfer. = 1, x resume transfer after a read/write mbuf operation. iicstus (r) : iic interface status register. wadrb = 1 the data in rcbbuf is word address. slvrwb = 1 current transfer is slave transmit = 0 current transfer is slave receive sackin = 1 the external iic host respond nack. slvs = 1 the slave block has detected a start, cleared when stop detected. mackin = 1 master iic bus error, no ack received from the slave iic device. = 0 ack received from the slave iic device.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 18 - april 2002 intflg (w) : interrupt flag. a interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. slvbmi = 1 no action. = 0 clears slvbmi flag. stopi = 1 no action. = 0 clears stopi flag. restai = 1 no action. = 0 clears restai flag. wslva1i = 1 no action. = 0 clears wslva1i flag. wslva2i = 1 no action. = 0 clears wslva2i flag. mbufi = 1 no action. = 0 clears master iic bus interrupt flag (mbufi). intflg (r) : interrupt flag. txbi = 1 indicates the txbbuf need a new data byte, cleared by writing txbbuf. rcbi = 1 indicates the rcbbuf has received a new data byte, cleared by reading rcbbuf. slvbmi = 1 indicates the slave iic address b match condition. stopi = 1 indicates the slave iic has detected a stop condition for hscl1/hsda1 pins. restai = 1 indicates the slave iic has detected a repeat start condition for hscl1/hsda1 pins. wslva1i = 1 indicates the slave a1 iic has detected a stop condition of write mode. wslva2i = 1 indicates the slave a2 iic has detected a stop condition of write mode. mbufi = 1 indicates a byte is sent/received to/from the master iic bus. inten (w) : interrupt enable. etxbi = 1 enables txbbuf interrupt. ercbi = 1 enables rcbbuf interrupt. eslvbmi = 1 enables slave address b match interrupt. estopi = 1 enables iic bus stop interrupt. erestai = 1 enables iic bus repeat start interrupt. ewslva1i = 1 enables slave a1 iic bus stop of write mode interrupt. ewslva2i = 1 enables slave a2 iic bus stop of write mode interrupt. embufi = 1 enables master iic bus interrupt. mbuf (w) : master iic data shift register, after start and before stop condition, write this register resumes MTV412M's transmission to the iic bus. mbuf (r) : master iic data shift register, after start and before stop condition, read this register resumes MTV412M's reception from the iic bus. ddcctra1 (w) : ddc interface control register for hscl1, hsda1 pins. ddc1en = 1 enables ddc1 data transfer in ddc1 mode. = 0 disables ddc1 data transfer in ddc1 mode. en128w = 1 the lower 128 bytes (00-7f) of ddcram1 can be written by iic master. = 0 the lower 128 bytes (00-7f) of ddcram1 cannot be written by iic master. en256w = 1 the higher 128 bytes (80-ff) of ddcram1 can be written by iic master. = 0 the higher 128 bytes (80-ff) of ddcram1 cannot be written by iic master. only128 = 1 the slavea1 always accesses edid data from the lower 128 bytes of ddcram1. = 0 the slavea1 accesses edid data from the whole 256 bytes ddcram1. slva1bs1,slva1bs0 : slave iic block a1's slave address length.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 19 - april 2002 = 1,0 5-bit slave address. = 0,1 6-bit slave address. = 0,0 7-bit slave address. slva1adr (w) : slave iic block a1's enable and address. enslva1= 1 enables slave iic block a1. = 0 disables slave iic block a1. bit6-0 : slave iic address a1 to which the slave block should respond. rcbbuf (r) : slave iic block b receives data buffer. txbbuf (w) : slave iic block b transmits data buffer. slvbadr (w) : slave iic block b's enable and address. enslvb = 1 enables slave iic block b. = 0 disables slave iic block b. bit6-0 : slave iic address b to which the slave block should respond. ddcctra2 (w) : ddc interface control register for hscl2, hsda2 pins. ddc1en = 1 enables ddc1 data transfer in ddc1 mode. = 0 disables ddc1 data transfer in ddc1 mode. en128w = 1 the lower 128 bytes (00-7f) of ddcram2 can be written by iic master. = 0 the lower 128 bytes (00-7f) of ddcram2 cannot be written by iic master. en256w = 1 the higher 128 bytes (80-ff) of ddcram2 can be written by iic master. = 0 the higher 128 bytes (80-ff) of ddcram2 cannot be written by iic master. only128 = 1 the slavea2 always accesses edid data from the lower 128 bytes of ddcram2. = 0 the slavea2 accesses edid data from the whole 256 bytes ddcram2. slva2bs1,slva2bs0 : slave iic block a2's slave address length. = 1,0 5-bit slave address. = 0,1 6-bit slave address. = 0,0 7-bit slave address. slva2adr (w) : slave iic block a2's enable and address. enslva2= 1 enables slave iic block a2. = 0 disables slave iic block a2. bit6-0 : slave iic address a2 to which the slave block should respond. 8. low power reset (lvr) & watchdog timer when the voltage level of power supply is below 3.8v(+/-0.2v) / 2.5v(+/-0.15v) in 5v / 3.3v applications for a specific period of time, the lvr generates a chip reset signal. after the power supply is above 3.8v(+/- 0.2v) / 2.5v(+/-0.15v) in 5v / 3.3v applications, lvr maintains in reset state for 144 x'tal cycle to guarantee the chip exit reset condition with a stable x'tal oscillation. the watchdog timer automatically generates a device reset when it is overflowed. the interval of overflow is 0.25 sec x n, where n is a number from 1 to 8, and can be programmed via register wdt(2:0). the timer function is disabled after power on reset, users can activate this function by setting wen, and clear the timer by setting wclr. 9. a/d converter the mtv312m is equipped with four vdd range 8-bit a/d converters. so if the vdd = 5v/3.3v, and then the adc conversion range is 5v/3.3v, s/w can select the current convert channel by setting the sadc1/sadc0 bit. the refresh rate for the adc is osc freq./1536 (128us for 12mhz x'tal).
myson-century technology MTV412M (rev 0.9) revision 0.9 - 20 - april 2002 the adc compares the input pin voltage with internal vdd*n/64 voltage (where n = 0 - 255). the adc output value is n when pin voltage is greater than vdd*n/255 and smaller than vdd*(n+1)/255. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc f10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc f10h (r) adc convert result wdt f18h (w) wen wclr wdt2 wdt1 wdt0 wdt (w) : watchdog timer control register. wen = 1 enables watchdog timer. wclr = 1 clears watchdog timer. wdt2: wdt0 = 0 overflow interval = 8 x 0.25 sec. = 1 overflow interval = 1 x 0.25 sec. = 2 overflow interval = 2 x 0.25 sec. = 3 overflow interval = 3 x 0.25 sec. = 4 overflow interval = 4 x 0.25 sec. = 5 overflow interval = 5 x 0.25 sec. = 6 overflow interval = 6 x 0.25 sec. = 7 overflow interval = 7 x 0.25 sec. adc (w) : adc control. enadc = 1 enables adc. sadc0 = 1 selects adc0 pin input. sadc1 = 1 selects adc1 pin input. sadc2 = 1 selects adc2 pin input. sadc3 = 1 selects adc3 pin input. adc (r) : adc convert result. 11. in system programming function (isp) the flash memory can be programmed by a specific writer in parallel mode, or by iic host in serial mode while the system is working. the features of isp are outlined as below: 1. single 3.3v power supply for program/erase/verify. 2. block erase: 1024 bytes for program code, 10ms 3. whole flash erase (blank): 10ms 4. byte/word programming cycle time: 60us per byte 5. read access time: 50ns 6. only one two-pin iic bus (shared with ddc2) is needed for isp in user/factory mode. 7. iic bus clock rates up to 140khz. 8. whole 128k-byte flash programming within 12 sec. 9. crc check provides 100% coverage for all single/double bit errors. there are two methods to enter the isp mode which are described as below: method 1). the valid isp slave address and compared data are transmitted method 2). write 93h to isp enable register (ispen) reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ispslv f0bh(w) isp slave address ispen f0ch(w) write 93h to enable isp mode ispslv (w) : isp slave iic's address. bit7-2 : isp slave iic's address to which the isp block should respond. the default value is 100101. ispen (w) : write 93h to enable isp mode for isp enable method 2.
myson-century technology MTV412M (rev 0.9) revision 0.9 - 21 - april 2002 memory map of xfr reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr f00h (r/w) ddc2 macko p s iicstus f01h (r) wadrb slvrwb sackin slvs mackin intflg f03h (r) txbi rcbi slvbmi stopi restai wslvai mbufi intflg f03h (w) slvbmi stopi restai wslvai mbufi inten f04h (w) etxbi ercbi eslvbmi estopi erestai ewslvai embufi mbuf f05h (r/w) master iic receives/transmits data buffer ddcctr f06h (w) ddc1en en128w en256w only128 slvabs1 slvabs0 slvaadr f07h (w) enslva slave a iic address rcbbuf f08h (r) slave b iic receives buffer txbbuf f08h (w) slave b iic transmits buffer slvbadr f09h (w) enslvb slave b iic address ispslv f0bh(w) isp slave address ispen f0ch(w) write 93h to enable isp mode ispcmp1 f0dh(w) isp compared data 1 [7:0] ispcmp2 f0eh(w) isp compared data 2 [7:0] ispcmp3 f0fh(w) isp compared data 3 [7:0] adc f10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc f10h (r) adc convert result wdt f18h (w) wen wclr wdt2 wdt1 wdt0 da0 f20h(r/w) pulse width of pwm dac 0 da1 f21h(r/w) pulse width of pwm dac 1 da2 f22h(r/w) pulse width of pwm dac 2 da3 f23h(r/w) pulse width of pwm dac 3 da4 f24h(r/w) pulse width of pwm dac 4 da5 f25h(r/w) pulse width of pwm dac 5 da6 f26h(r/w) pulse width of pwm dac 6 da7 f27h(r/w) pulse width of pwm dac 7 da8 f28h(r/w) pulse width of pwm dac 8 da9 f29h(r/w) pulse width of pwm dac 9 da10 f2ah(r/w) pulse width of pwm dac 10 da11 f2bh(r/w) pulse width of pwm dac 11 da12 f2ch(r/w) pulse width of pwm dac 12 da13 f2dh(r/w) pulse width of pwm dac 13 port5 f30h(r/w) p50 port5 f31h(r/w) p51 port5 f32h(r/w) p52 port5 f33h(r/w) p53 port5 f34h(r/w) p54 port5 f35h(r/w) p55 port5 f36h(r/w) p56 port6 f38h(r/w) p60 port6 f39h(r/w) p61 port6 f3ah(r/w) p62 port6 f3bh(r/w) p63 port6 f3ch(r/w) p64 port6 f3dh(r/w) p65 port6 f3eh(r/w) p66 port6 f3fh(r/w) p67 hvstus f40h(r) cvpre hpol vpol hpre vpre hoff voff hcnth f41h(r) hovf hf13 hf12 hf11 hf10 hf9 hf8
myson-century technology MTV412M (rev 0.9) revision 0.9 - 22 - april 2002 hcntl f42h(r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth f43h(r) vovf vf11 vf10 vf9 vf8 vcntl f44h(r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 hvctr0 f40h(w) c1 c0 nohins hbpl vbpl hvctr3 f43h(w) clpeg clppo clpw2 clpw1 clpw0 hvctr4 f44h(w) vcpol df1 df0 intflg f48h(r/w) hprchg vprchg hplchg vplchg hfchg vfchg vsync inten f49h(w) ehpr evpr ehpl evpl ehf evf evsync padmod f50h(w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod f51h(w) p56e p55e p54e p53e p52e p51e p50e padmod f52h(w) hiic1e iiice hiic2e ckoe hclpe p42e p41e p40e padmod f53h(w) p56oe p55oe p54oe p53oe p52oe p51oe p50oe padmod f54h(w) p67oe p66oe p65oe p64oe p63oe p62oe p61oe p60oe padmod f55h(w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 option f56h(w) pwmf div253 fclke enscl msel miicf1 miicf0 port4 f58h(w) p40 port4 f59h(w) p41 port4 f5ah(w) p42 padmod f5eh(w) p74e p73e p72e p71e p70e padmod f5fh(w) p77oe p76oe p75oe p74oe p73oe p72oe p71oe p70oe port7 f70h(r/w) p70 port7 f71h(r/w) p71 port7 f72h(r/w) p72 port7 f73h(r/w) p73 port7 f74h(r/w) p74 port7 f75h(r/w) p75 port7 f76h(r/w) p76 port7 f77h(r/w) p77 epadrh ff1h(w) eadr10 eadr9 eadr8 epadrl ff2h(w) eadr7 eadr6 eadr5 eadr4 eadr3 eadr2 eadr1 eadr0 epdata ff3h(r/w) edata [7:0] intflg ff4h(r/w) epbpf inten ff5h(w) eepbpf
myson-century technology MTV412M (rev 0.9) revision 0.9 - 23 - april 2002 electrical parameters 1. absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +6.0 v maximum input voltage (hsync, vsync & open-drain pins) vin1 -0.3 to 5v+0.3 v maximum input voltage (other pins) vin2 -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 o c maximum storage temperature tstg -25 to +125 o c 2. allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol condition min. max. unit 5v applications 4.5 5.5 v supply voltage vdd 3.3v applications 3.0 3.6 v vih1 5v applications 0.4 x vdd vdd +0.3 v input "h" voltage vih2 3.3v applications 0.6 x vdd vdd +0.3 v vil1 5v applications -0.3 0.2 x vdd v input "l" voltage vil2 3.3v applications -0.3 0.3 x vdd v operating freq. fopg - 15 mhz 3. dc characteristics at: ta=0 to 70 o c, vdd=5.0v/3.3v, vss=0v name symbol condition min. typ. max. unit voh1 vdd=5v, ioh=0ua 4 v output "h" voltage, open drain pin voh2 vdd=3.3v, ioh=0ua 2.65 v voh3 vdd=5v, ioh=-50ua 4 v output "h" voltage, 8051 i/o port pin voh4 vdd=3.3v, ioh=-50ua 2.65 v voh5 vdd=5v, ioh=-4ma 4 v output "h" voltage, cmos output voh6 vdd=3.3v, ioh=-4ma 2.65 v output "l" voltage vol iol=5ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 ua rst pull-down resistor rrst vdd=5v 150 250 kohm pin capacitance cio 15 pf
myson-century technology MTV412M (rev 0.9) revision 0.9 - 24 - april 2002 4. ac characteristics at: ta=0 to 70 o c, vdd=5.0v/3.3v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 12 mhz pwm dac frequency fda fxtal=12mhz 46.875 94.86 khz hs input pulse width thipw fxtal=12mhz 0.3 7.5 us vs input pulse width tvipw fxtal=12mhz 3 us hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=12mhz 8 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 us test mode condition in normal application, users should avoid the MTV412M entering its test mode or writer mode, outlined as follows, adding pull-up resistor to da8 and da9 pins is recommended. test mode a: reset=1 & da9=1 & da8=0 & p4.2=0 test mode b: reset's falling edge & da9=1 & da8=0 & p4.2=1 writer mode: reset=1 & da9=0 & da8=1
myson-century technology MTV412M (rev 0.9) revision 0.9 - 25 - april 2002 package dimension 1. 42 pin sdip unit: mm 2. 44 pin plcc unit: pin #1 hole 0.653 +/-0.003 0.690 +/-0.005 0.690 +/-0.005 0.653 +/-0.003 0.045*45 0 0.180 max. 0.020 min. 0.610 +/-0.02 0.500 0.070 0.070 7 0 typ. 0.010 0.050 typ. 0.013~0.021 typ. 0.026~0.032 typ. dimension in mm symbol min nom max a 3.937 4.064 4.2 a1 1.78 1.842 1.88 b1 0.914 1.270 1.118 d 36.78 36.83 36.88 e1 13.945 13.970 13.995 f 15.19 15.240 15.29 eb 15.24 16.510 17.78 0 7.5 15 15.494mm +/- 0.254 13.868mm +/- 0.102 16.256mm +/- 0.508 0.254m m +/-0.102 5 o ~7 0 6 o +/- 3 o
myson-century technology MTV412M (rev 0.9) revision 0.9 - 26 - april 2002 ordering information standard configurations: prefix part type package type rom size (k) mtv 412m s: sdip v: plcc f: pqfp 128

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